View MTV012E_1285963.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

MYSON TECHNOLOGY
MTV012E
8051 Embedded CRT Monitor Controller OTP Version
FEATURES
8051 core. 256 bytes internal RAM. 8K bytes program EPROM. 14 channels 12V open drain PWM DAC, 10 dedicated channels and 4 channels shared with I/O pin. 20 bi-direction I/O pin, 12 dedicated pin, 4 shared with DAC, 4 shared with DDC/IIC interface. 3 output pin shared with H/V sync output and self test output pins. SYNC processor for composite separation, polarity and frequency check, and polarity adjust. Built-in monitor self test pattern generator. Built-in Low Power Reset circuit. IIC interface for DDC1/DDC2B and EEPROM, only one EEPROM needed to store DDC1/DDC2B and display mode information. Watch dog timer with programmable interval. 40 pin PDIP package.
GENERAL DESCRIPTION
The MTV012E micro-controller is an 8051 CPU core-embedded device specially tailored to CRT monitor applications. It includes an 8051 CPU core, 256-byte SRAM, 14 built-in PWM DACs, DDC1/DDC2B interface, 24Cxx series EEPROM interface and an 8K-byte internal program EPROM.
BLOCK DIAGRAM
STOUT P1.0-7 X1 P0.0-7 RD WR P0.0-7 RD WR
XFR
HSYNC
H/VSYNC CONTROL
VSYNC HBLANK VBLANK
X2
8051 CORE
INT1
WATCH-DOG TIMER
RST
P2.0-3 P3.0-P3.2
RST
14 CHANNEL PWM DAC
DA0-9
DA10-13 P3.4 P2.4-7
HSCL HSDA
DDC 1/2 B & FIFO INTERFACE
ISCL
IIC INTERFACE
ISDA
This datasheet contains new product information. Myson Technology reserves the rights to modify the product specification without notice. No liability is assumed as a result of the use of this product. No rights under any patent accompany the sale of the product. MTV012E Revision 1.2 12/23/1998 1/14
MYSON TECHNOLOGY
1.0 PIN CONNECTION
P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7 RST HSCL/P3.0/Rxd HSDA/P3.1/Txd ISDA/P3.2/INT0 HSYNC ISCL/P3.4/T0 VSYNC HBLANK/P4.1 VBLANK/P4.0 X2 X1 VSS VDD DA0 DA1 DA2 DA3 DA4 DA5 DA6 DA7 DA8 DA9 STOUT/P4.2 DA10/P2.7 DA11/P2.6 DA12/P2.5 DA13/P2.4 P2.3 P2.2 P2.1 P2.0/INT0
MTV012E
MTV012E
2.0 PIN DESCRIPTION
Name P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7 RST HSCL/P3.0/Rxd HSDA/P3.1/Txd ISDA/P3.2/INT0 HSYNC ISCL/P3.4/T0 VSYNC HBLANK/P4.1 VBLANK/P4.0 X2 X1 VSS P2.0/INT0 Type I/O I/O I/O I/O I/O I/O I/O I/O I I/O I/O I/O I I/O I O O O I I/O Pin# 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 Description General purpose I/O General purpose I/O General purpose I/O General purpose I/O General purpose I/O General purpose I/O General purpose I/O General purpose I/O Active high reset IIC clock / General purpose I/O / Rxd IIC data / General purpose I/O / Txd IIC data / General purpose I/O / INT0 Horizontal SYNC or composite SYNC IIC clock / General purpose I/O / T0 Vertical SYNC Horizontal blank / General purpose output Vertical blank / General purpose output Oscillator output Oscillator input Ground General purpose I/O / INT0
MTV012E Revision 1.2 12/23/1998 2/14
MYSON TECHNOLOGY
P2.1 P2.2 P2.3 DA13/P2.4 DA12/P2.5 DA11/P2.6 DA10/P2.7 STOUT/P4.2 DA9 DA8 DA7 DA6 DA5 DA4 DA3 DA2 DA1 DA0 VDD I/O I/O I/O I/O I/O I/O I/O O O O O O O O O O O O 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
MTV012E
General purpose I/O General purpose I/O General purpose I/O PWM DAC output / General purpose I/O (open-drain) PWM DAC output / General purpose I/O (open-drain) PWM DAC output / General purpose I/O (open-drain) PWM DAC output / General purpose I/O (open-drain) Self-test video output / General purpose output PWM DAC output (open-drain) PWM DAC output (open-drain) PWM DAC output (open-drain) PWM DAC output (open-drain) PWM DAC output (open-drain) PWM DAC output (open-drain) PWM DAC output (open-drain) PWM DAC output (open-drain) PWM DAC output (open-drain) PWM DAC output (open-drain) Positive power supply
3.0 FUNCTIONAL DESCRIPTIONS
1. 8051 CPU Core MTV012E includes all the 8051 functions with the following exceptions: 1.1 PSEN, ALE, RD and WR pins are disabled. The external RAM access is restricted to XFRs within MTV012E. 1.2 Port0, port3.3 and ports3.5 ~ 3.7 are not general purpose I/O ports. They are dedicated to monitoring control/DAC pins. 1.3 INT1 and T1 input pins are not provided. 1.4 Ports2.4 ~ 2.7 are shared with DAC pins; ports3.0 ~ 3.2 and port3.4 are shared with monitor control pins. In addition, there are 2 timers, 5 interrupt sources and a serial interface compatible with the standard 8051. The Txd/Rxd (P3.0/P3.1) pins are shared with the DDC interface. INT0/T0 pins are shared with the IIC interface. An extra option can be used to switch the INT0 source from P3.2 to P2.0. This feature maintains an external interrupt source when the IIC interface is enabled. Note: All registers listed in this document reside in the external RAM area (XFR). For the internal RAM memory map, please refer to the 8051 spec.
reg name PADMOD addr 30h (w) bit7 SINT0 bit6 X bit5 DDCE bit4 IICE bit3 DA13E bit2 DA12E bit1 DA11E bit0 DA10E
SINT0 = 1 =0 DDCE = 1 =0 IICE =1 =0 DA13E = 1 =0 DA12E = 1 =0
INT0 source is pin #21. INT0 source is pin #12. Pin #10 is HSCL; pin #11 is HSDA. Pin #10 is P3.0/Rxd; pin #11 is P3.1/Txd. Pin #12 is ISDA; pin #14 is ISCL. Pin #12 is P3.2/(INT0*); pin #14 is P3.4/T0. Pin #25 is DA13. Pin #25 is P2.4. Pin #26 is DA12. Pin #26 is P2.5.
MTV012E Revision 1.2 12/23/1998 3/14
MYSON TECHNOLOGY
DA11E = 1 Pin #27 is DA11. =0 Pin #27 is P2.6. DA10E = 1 Pin #28 is DA10. =0 Pin #28 is P2.7. * SINT0 should be 0 in this case. 2. External Special Function Registers (XFR)
MTV012E
The XFR is a group of registers allocated in the 8051 external RAM area. Most of the registers are used for monitor control or PWM DAC. The program can initialize Ri value and use "MOVX" instruction to access these registers. 3. PWM DAC Each D/A converter's output pulse width is controlled by an 8-bit register in the XFR. The frequency of these outputs is (Xtal frequency)/253 or (Xtal frequency)/256, selected by DIV253. If DIV253=1, writing FDH/FEH/FFH to the DAC register generates a stable high output. If DIV253=0, the output will pulse low at least once even if the DAC register's content is FFH. Writing 00H to the DAC register generates stable low output.
reg name DA0 DA1 DA2 DA3 DA4 DA5 DA6 DA7 DA8 DA9 DA10 DA11 DA12 DA13 WDT addr 20h (r/w) 21h (r/w) 22h (r/w) 23h (r/w) 24h (r/w) 25h (r/w) 26h (r/w) 27h (r/w) 28h (r/w) 29h (r/w) 2Ah (r/w) 2Bh (r/w) 2Ch (r/w) 2Dh (r/w) 80h bit7 DA0b7 DA1b7 DA2b7 DA3b7 DA4b7 DA5b7 DA6b7 DA7b7 DA8b7 DA9b7 DA10b7 DA11b7 DA12b7 DA13b7 WEN bit6 DA0b6 DA1b6 DA2b6 DA3b6 DA4b6 DA5b6 DA6b6 DA7b6 DA8b6 DA9b6 DA10b6 DA11b6 DA12b6 DA13b6 WCLR bit5 DA0b5 DA1b5 DA2b5 DA3b5 DA4b5 DA5b5 DA6b5 DA7b5 DA8b5 DA9b5 DA10b5 DA11b5 DA12b5 DA13b5 CLRDDC bit4 DA0b4 DA1b4 DA2b4 DA3b4 DA4b4 DA5b4 DA6b4 DA7b4 DA8b4 DA9b4 DA10b4 DA11b4 DA12b4 DA13b4 DIV253 bit3 DA0b3 DA1b3 DA2b3 DA3b3 DA4b3 DA5b3 DA6b3 DA7b3 DA8b3 DA9b3 DA10b3 DA11b3 DA12b3 DA13b3 X bit2 DA0b2 DA1b2 DA2b2 DA3b2 DA4b2 DA5b2 DA6b2 DA7b2 DA8b2 DA9b2 DA10b2 DA11b2 DA12b2 DA13b2 WDT2 bit1 DA0b1 DA1b1 DA2b1 DA3b1 DA4b1 DA5b1 DA6b1 DA7b1 DA8b1 DA9b1 DA10b1 DA11b1 DA12b1 DA13b1 WDT1 bit0 DA0b0 DA1b0 DA2b0 DA3b0 DA4b0 DA5b0 DA6b0 DA7b0 DA8b0 DA9b0 DA10b0 DA11b0 DA12b0 DA13b0 WDT0
DA0 (r/w) : The output pulse width control for DA0. DA1 (r/w) : The output pulse width control for DA1. DA2 (r/w) : The output pulse width control for DA2. DA3 (r/w) : The output pulse width control for DA3. DA4 (r/w) : The output pulse width control for DA4. DA5 (r/w) : The output pulse width control for DA5. DA6 (r/w) : The output pulse width control for DA6. DA7 (r/w) : The output pulse width control for DA7. DA8 (r/w) : The output pulse width control for DA8. DA9 (r/w) : The output pulse width control for DA9. DA10 (r/w) : The output pulse width control for DA10. DA11 (r/w) : The output pulse width control for DA11. DA12 (r/w) : The output pulse width control for DA12. DA13 (r/w) : The output pulse width control for DA13. WDT (w) : Watchdog timer & special control bit. DIV253 = 1 The PWM DAC output frequency is (Xtal frequency)/253. =0 The PWM DAC output frequency is (Xtal frequency)/256. *1. All D/A converters are centered with value 80h after power-on.
MTV012E Revision 1.2 12/23/1998 4/14
MYSON TECHNOLOGY
4. H/V SYNC Processing
MTV012E
The H/V SYNC processing block performs the functions of composite signal separation, SYNC input presence check, frequency counting, and polarity detection and control, as well as protection of VBLANK output while VSYNC speeds up to a high DDC communication clock rate. The present and frequency function block treat any pulse shorter than 1 OSC period as noise. 4.1 Composite SYNC Separate MTV012E continuously monitors the input HSYNC. If the vertical SYNC pulse can be extracted from the input, a CVpre flag is set and the user can select the extracted "CVSYNC" for the source of polarity check, frequency count and VBLANK. The CVSYNC will have a 10-16 us delay compared to the original signal. The delay depends on the OSC frequency and composite mix method. 4.2 H/V Frequency Counter MTV012E can discriminate between HSYNC/VSYNC frequency and saves the information in XFRs. The 15-bit H counter counts the time of the 64xHSYNC period, but only 11 upper bits are loaded into the HCNTH/HCNTL latch. The 11-bit output value will be (2/Hfreq) / (1/OSCfreq), updated once per VSYNC/CVSYNC period when VSYNC/CVSYNC is present, or continuously updated when VSYNC/CVSYNC is not present. The 14-bit V counter counts the time between 2 VSYNC pulses, but only 9 upper bits are loaded into the VCNTH/VCNTL latch. The 9-bit output value will be (1/Vfreq) / (512/OSCfreq), updated every VSYNC/CVSYNC period. An extra overflow bit indicates the condition of H/V counter overflow. The VFchg/HFchg interrupt is active when VCNT/HCNT value changes or overflows. Tables 4.2.1 and 4.2.2 show the HCNT/VCNT value under the 8MHz/12MHz OSC operations.
4.2.1 H-Freq Table
Output Value (11 bits) 8MHz OSC (hex / dec) 12MHz OSC (hex / dec) 1 30 215h / 533 320h / 800 2 31.5 1FBh / 507 2F9h / 761 3 33.5 1DDh /477 2CCh / 716 4 35.5 1C2h / 450 2A4h / 676 5 36.8 1B2h / 434 28Ch / 652 6 38 1A5h / 421 277h / 631 7 40 190h / 400 258h / 600 8 48 14Dh / 333 1F4h / 500 9 50 140h / 320 1E0h / 480 10 57 118h / 280 1A5h / 421 11 60 10Ah / 266 190h / 400 12 64 0FAh / 250 177h / 375 13 100 0A0h / 160 0F0h / 240 *1. The H-Freq output (HF10 - HF0) is valid. *2. The tolerance deviation is + 1 LSB. H-Freq(KHZ)
4.2.2 V-Freq Table
V-Freq(Hz) 1 2 3 4 56.25 59.94 60 60.32 Output Value (9 bits) 8MHz OSC (hex / dec) 12MHz OSC (hex / dec) 115h / 277 1A0h / 416 104h / 260 187h / 391 104h / 260 186h / 390 103h / 259 184h / 388
MTV012E Revision 1.2 12/23/1998 5/14
MYSON TECHNOLOGY
5 60.53 102h / 258 6 66.67 0EAh / 234 7 70.069 0DEh / 222 8 70.08 0DEh / 222 9 72 0D9h /217 10 72.378 0D7h / 215 11 72.7 0D6h / 214 12 87 0B3h / 179 *1. The V-Freq output (VF8 - VF0) is valid. *2. The tolerance deviation is + 1 LSB. 183h / 387 15Fh / 351 14Eh / 334 14Eh / 334 145h / 325 143h / 323 142h / 322 10Dh / 269
MTV012E
4.3 H/V Present Check The H present function checks the input HSYNC pulse; the Hpre flag is set when HSYNC is over 10KHz or cleared when HSYNC is under 10Hz. The V present function checks the input VSYNC pulse; the Vpre flag is set when VSYNC is over 40Hz or cleared when VSYNC is under 10Hz. The control bit "PREFS" selects the time base for these functions. The HPRchg interrupt is set when the Hpre value changes. The VPRchg interrupt is set when the Vpre/CVpre values change. However, the CVpre flag interrupt may be disabled when S/W disables the composite function. 4.4 H/V Polarity Detection The polarity functions detect the input HSYNC/VSYNC high and low pulse duty cycle. If the high pulse duration is longer than that of the low pulse, the negative polarity is asserted; otherwise, positive polarity is asserted. The HPLchg interrupt is set when the Hpol value changes. The VPLchg interrupt is set when the Vpol value changes. 4.5 Output HBLANK/VBLANK Control and Polarity Adjustment HBLANK is the MUX output of HSYNC and the self-test horizontal pattern. The VBLANK is the MUX output of VSYNC, CVSYNC and the self-test vertical pattern. The MUX selection and output polarity are S/W controllable. The VBLANK output is cut off when VSYNC frequency is over 200Hz or 133Hz depends on 8MHz/12MHz OSC selection. HBLANK/VBLANK shares the output pin with P4.1/ P4.0. 4.6 Self-Test Pattern Generator This generator can generate 4 display patterns for testing purposes: positive cross-hatch, negative cross-hatch, full white and full black (shown in the following figure). It was originally designed to support monitor manufacturers to do a burn-in test, or offer the end-user a reference to check the monitor. The generator's output STOUT shares the output pin with P4.2.
Display Region
Self-Test Patterns (1)
MTV012E Revision 1.2 12/23/1998 6/14
MYSON TECHNOLOGY
MTV012E
Self-Test Patterns (2) 4.7 H/V Sync Processor Register
Present Check Digital Filter Frequency Count Polarity Check
Vpre
Vfreq
Vpol VBpl
VSYNC
Vself
High Frequency Mask
VBLANK
CVSYNC
Polarity Check & Sync Seperator
Hself Hpol
Present Check
CVpre
HBpl
HBLANK
Digital Filter Present Check & Frequency Count
Hpre Hfreq
HSYNC
H/V SYNC Processor Block Diagram
reg name PSTUS HCNTH HCNTL VCNTH VCNTL PCTR0 PCTR2 P4OUT INTFLG INTEN addr 40h (r) 41h (r) 42h (r) 43h (r) 44h (r) 40h (w) 42h (w) 44h (w) 50h (r/w) 60h (w) bit7 CVpre Hovf HF7 Vovf VF7 C1 X X HPRchg EHPR bit6 X X HF6 X VF6 C0 X X VPRchg EVPR bit5 Hpol X HF5 X VF5 HVsel X X HPLchg EHPL bit4 Vpol X HF4 X VF4 STOsel Selft X VPLchg EVPL bit3 Hpre X HF3 X VF3 PREFS STbsh X HFchg EHF bit2 Vpre HF10 HF2 X VF2 HALFV Rt1 P42 VFchg EVF bit1 Hoff HF9 HF1 X VF1 HBpl Rt0 P41 FIFOI EFIFO bit0 Voff HF8 HF0 VF8 VF0 VBpl STF P40 MI EMI
PSTUS (r): The status of polarity, present and static level for HSYNC and VSYNC. CVpre = 1 The extracted CVSYNC is present. =0 The extracted CVSYNC is not present. Hpol =1 HSYNC input is positive polarity.
MTV012E Revision 1.2 12/23/1998 7/14
MYSON TECHNOLOGY
=0 HSYNC input is negative polarity. =1 VSYNC (CVSYNC) is positive polarity. =0 VSYNC (CVSYNC) is negative polarity. Hpre = 1 HSYNC input is present. =0 HSYNC input is not present. Vpre =1 VSYNC input is present. =0 VSYNC input is not present. Hoff* = 1 HSYNC input's off-level is high. =0 HSYNC input's off-level is low. Voff* = 1 VSYNC input's off-level is high. =0 VSYNC input's off-level is low. *Hoff and Voff are valid when Hpre=0 or Vpre=0. Vpol HCNTH (r) : Hovf
MTV012E
H-Freq counter's high bits. =1 H-Freq counter overflows; this bit is cleared by H/W when condition removed. HF10 - HF8 : 3 high bits of H-Freq counter. H-Freq counter's low bits. V-Freq counter's high bits. =1 V-Freq counter overflows; this bit is cleared by H/W when condition removed. High bit of V-Freq counter. V-Freq counter's low bits.
HCNTL (r) : VCNTH (r) : Vovf VF8 : VCNTL (r) :
PCTR0 (w) : SYNC processor control register 0. C1, C0 = 1,1 Selects CVSYNC as the polarity, freq and VBLANK source. = 1,0 Selects VSYNC as the polarity, freq and VBLANK source. = 0,0 Disables composite function (MTV012 compatible mode). = 0,1 H/W auto switch to CVSYNC when CVpre=1 and VSpre=0. HVsel = 1 Pin #16 is P41, pin #17 is P40. =0 Pin #16 is HBLANK, pin #17 is VBLANK. STOsel = 1 Pin #29 is P42. =0 Pin #29 is STOUT. PREFS = 0 Selects 8MHz OSC as H/V present check and self-test pattern time base. =1 Selects 12MHz OSC as H/V present check and self-test pattern time base. HALFV = 1 VBLANK is half frequency output of VSYNC. HBpl = 1 Negative polarity HBLANK output. =0 Positive polarity HBLANK output. VBpl = 1 Negative polarity VBLANK output. =0 Positive polarity VBLANK output. PCTR2 (w) : Selft Self-test pattern generator control. =1 Enables generator. =0 Disables generator. STbsh = 1 63.5KHz (horizontal) output selected. =0 31.75KHz (horizontal) output selected. Rt1,Rt0 = 0,0 Positive cross-hatch pattern output. = 0,1 Negative cross-hatch pattern output. = 1,0 Full white pattern output. = 1,1 Full black pattern output.
MTV012E Revision 1.2 12/23/1998 8/14
MYSON TECHNOLOGY
STF P4OUT (w) : INTFLG (w) : =1 Enables STOUT output. =0 Disables STOUT output. Port 4 data output value.
MTV012E
Interrupt flag. An interrupt event will set its individual flag, and, if the corresponding interrupt enable bit is set, the 8051 core's INT1 source will be driven by a zero level. Software MUST clear this register while serving the interrupt routine. HPRchg= 1 No action. =0 Clears HSYNC presence change flag. VPRchg= 1 No action. =0 Clears VSYNC presence change flag. HPLchg= 1 No action. =0 Clears HSYNC polarity change flag. VPLchg = 1 No action. =0 Clears VSYNC polarity change flag. HFchg = 1 No action. =0 Clears HSYNC frequency change flag. VFchg = 1 No action. =0 Clears VSYNC frequency change flag.
INTFLG (r) : Interrupt flag. HPRchg= 1 Indicates an HSYNC presence change. VPRchg= 1 Indicates a VSYNC presence change. HPLchg= 1 Indicates an HSYNC polarity change. VPLchg = 1 Indicates a VSYNC polarity change. HFchg = 1 Indicates an HSYNC frequency change or counter overflow. VFchg = 1 Indicates a VSYNC frequency change or counter overflow. INTEN (w) : EHPR EVPR EHPL EVPL EHF EVF Interrupt enabler. =1 Enables HSYNC presence change interrupt. =1 Enables VSYNC presence change interrupt. =1 Enables HSYNC polarity change interrupt. =1 Enables VSYNC polarity change interrupt. =1 Enables HSYNC frequency change / counter overflow interrupt. =1 Enables VSYNC frequency change / counter overflow interrupt.
5. DDC & IIC Interface 5.1 DDC1 Mode MTV012E enters DDC1 mode after Reset. In this mode, VSYNC is used as a data clock. The HSCL pin should remain at high. The data output to the HSDA pin is taken from 8 bytes of FIFO in MTV012E. MTV012E fetches the data byte from FIFO, then sends it in a 9-bit packet format which includes a null bit (=1) as packet separator. The software program should load EDID data (original stored in EEPROM) into FIFO and take care of the FIFO depth. FIFO sets the FIFOI (FIFO low interrupt) flag when there are fewer than N (N=2,3,4 or 5 controlled by LS1, LS0) bytes to be output to the HSDA pin. To prevent FIFO from emptying, software needs to write EDID data to FIFO as soon as FIFOI is set. On the other hand, FIFO sets the FIFOH flag when its capacity is full. Software should not write additional data to FIFO in such an instance. The FIFOI interrupt can be masked or enabled by an EFIFO control bit. A simple way to control FIFO is to set (LS1, LS0=1,0) and enable FIFOI interrupt, then software may load 4 bytes into FIFO each time a FIFOI interrupt arises. A special control bit "LDFIFO" can reduce the software effort when EDID data is stored in EEPROM. If LDFIFO=1, FIFO will be automatically loaded with MBUF data when software reads MBUF XFR.
MTV012E Revision 1.2 12/23/1998 9/14
MYSON TECHNOLOGY
MTV012E
5.2 DDC2B Mode MTV012E switches to DDC2B mode when it detects a high to low transition on the HSCL pin. Once MTV012E enters DDC2B mode, the host can access the EEPROM using IIC bus protocol as if the HSDA and HSCL are directly bypassed to ISDA and ISCL pins. MTV012E will return to DDC1 mode if HSCL is kept high for a 128-VSYNC clock period. However, it will 100K in DDC2B mode if a valid IIC access has been detected on the HSCL/HSDA bus. The DDC2 flag reflects the current DDC status; S/W may clear it by setting CLRDDC. The control bits M128/M256 are used to block the EEPROM write operation from the host if the address is over 128/256. 5.3 Master Mode IIC Function Block The master mode IIC block is connected to the ISDA and ISCL pins. The software program can access the external EEPROM through this interface. Since the EDID/VDIF data and the display information share the common EEPROM, precaution must be taken to avoid bus conflict. In DDC1 mode, the IIC interface is controlled by MTV012E only. In DDC2B mode, the host may access the EEPROM directly. Software can test the HSCL condition by reading the BUSY flag, which is set in case of HSCL=0. A summary of master IIC access is illustrated as follows:
5.3.1. To Write EEPROM 1. Write to MBUF the EEPROM slave address (bit 0 = 0). 2. Set S bit to Start. 3. After MTV012E transmits this byte, a MI interrupt will be triggered. 4. The program can write MBUF to transfer the next byte, or set the P bit to stop. * Please see the attachments about "Master IIC Transmission Timing". 5.3.2. To Read EEPROM 1. Write to MBUF the slave address (bit 0 = 1). 2. Set the S bit to Start. 3. After MTV012E transmits this byte, a MI interrupt will be triggered. 4. Set or reset the ACK flag according to the IIC protocol. 5. Read out to MBUF the useless byte in order to continue the data transfer. 6. After MTV012E receives a new byte, the MI interrupt is triggered again. 7. Reading MBUF also triggers the next receiving operation, but the P bit needs to be set before reading can terminate the operation. * Please see the attachments about the "Master IIC Timing Receiving".
5.4 Slave Mode IIC Function Block The slave mode IIC block can be connected to HSDA/HSCL pins or ISDA/ISCL pins, and selected by the SLVsel control bit. This block is receiving mode only. S/W may set the SLVADR register to determine the address range to which this block should respond. The block first detects an IIC slave address match condition, then issues a SLVMI interrupt. The data received from SDA is shifted onto the shift register and moved to the SLVBUF latch. The first byte loaded is the word address (the slave address is dropped). This block also generates a SLVBI each time the SLVBUF is loaded. If S/W can't read out the SLVBUF in time, the next byte will not be written to SLVBUF and the slave block returns NACK to the master. This feature guarantees the data integrity of communication. A WADR flag can tell S/W if the data in SLVBUF is a word address. * Please see the attachments about "Slave IIC Block Timing". 6. Low Power Reset (LVR) & Watchdog Timer When the voltage level of the power supply is below 4.0V for a specific time, the LVR will generate a chip reset signal. After the power supply is above 4.0V, LVR maintains the reset state for a 144 Xtal cycle to guarantee that the chip exit reset condition has a stable Xtal oscillation. The specific time of power supply in the low level is 3us and is adjustable by an external capacitor connected to the RST pin. The watchdog timer automatically generates a device reset when it overflows. The interval of overflow is 0.25 sec x N, in which N is a number from 1 to 8, and can be programmed via register WDT(2:0). The
MTV012E Revision 1.2 12/23/1998 10/14
MYSON TECHNOLOGY
MTV012E
timer function is disabled after power-on reset; the user can activate this function by setting WEN, and clear the timer by setting WCLR.
reg name MSTUS MBUF INTFLG MCTR INTEN FIFO WDT SLVCTR SLVSTUS SLVINT SLVBUF SLVADR addr 00h (r) 10h (r/w) 50h (r/w) 00h (w) 60h (w) 70h (w) 80h (w) 90h (w) 91h (r) 91h (w) 92h (r) 93h (w) bit7 X MBUF7 HPRchg LS1 EHPR FIFO7 WEN ENSLV WADR X SLVbuf7 SLVadr7 bit6 SCLERR MBUF6 VPRchg LS0 EVPR FIFO6 WCLR SLVsel SLVS X SLVbuf6 SLVadr6 bit5 DDC2 MBUF5 HPLchg LDFIFO EHPL FIFO5 CLRDDC ESLVBI SLVBI X SLVbuf5 SLVadr5 bit4 BERR MBUF4 VPLchg M256 EVPL FIFO4 DIV253 ESLVMI SLVMI SLVMI SLVbuf4 SLVadr4 bit3 HFREQ MBUF3 HFchg M128 EHF FIFO3 LVSEL X X X SLVbuf3 SLVadr3 bit2 FIFOH MBUF2 VFchg ACK EVF FIFO2 WDT2 X X X SLVbuf2 SLVadr2 bit1 FIFOL MBUF1 FIFOI P EFIFO FIFO1 WDT1 X X X SLVbuf1 SLVadr1 bit0 BUSY MBUF0 MI S EMI FIFO0 WDT0 X X X SLVbuf0 X
MCTR (w) : Master IIC interface control register. LS1, LS0 = 11 FIFOL is the status which has a FIFO depth of < 5. = 10 FIFOL is the status which has a FIFO depth of < 4. = 01 FIFOL is the status which has a FIFO depth of < 3. = 00 FIFOL is the status which has a FIFO depth of < 2. LDFIFO =1 FIFO will be written while S/W reads MBUF. M256 =1 Disables host writing EEPROM when address is over 256. M128 =1 Disables host writing EEPROM when address is over 128. ACK =1 In receiving mode, there is no acknowledgment by MTV012E. =0 In receiving mode, ACK is returned by MTV012E. S, P = ,0 Start condition when Master IIC is not transferring. = X, Stop condition when Master IIC is not transferring. = 1,X Will resume transfer after a read/write MBUF operation. = X,0 Forces HSCL low and occupies the IIC bus. * MTV012E uses a 100KHz clock to sample the S/P bit; any pulse should sustain at least 20us. * A write/read MBUF operation can be recognized only after 10us of the MI flag's rising edge. MSTUS (r) : Master IIC interface status register. SCLERR =1 The ISCL pin is pulled-low by other devices during the transfer, and cleared when S=0. DDC2 =1 DDC2B is active. =0 MTV012E remains in DDC1 mode. BERR =1 IIC bus error, no ACK received from the slave, updated every time when slave sends ACK on the ISDA pin. HFREQ =1 MTV012E detects a higher than 200Hz clock on the VSYNC pin. FIFOH =1 FIFO high indicated. FIFOL =1 FIFO low indicated. BUSY =1 Host drives the HSCL pin to low. * While writing FIFO, the FIFOH/FIFOL flag will reflect the FIFO condition after 30us. INTFLG (w) : Interrupt flag. An interrupt event will set its individual flag and, if the corresponding interrupt enable bit is set, the 8051 INT1 source will be driven by a zero level. Software MUST clear this register while serving the interrupt routine. FIFOI = 1 No action. =0 Clears FIFOI flag. MI =1 No action. =0 Clears Master IIC bus interrupt flag (MI).
MTV012E Revision 1.2 12/23/1998 11/14
MYSON TECHNOLOGY
MTV012E
INTFLG (r) : Interrupt flag. FIFOI = 1 Indicates the FIFO low condition; when EFIFO is set, MTV012E will be interrupted by INT1. MI =1 Indicates when a byte is sent/received to/from the IIC bus; when EMI is active, MTV012E will be interrupted by INT1. INTEN (w) : Interrupt enabler. EFIFO = 1 Enables FIFO interrupt. EMI =1 Enables master IIC bus interrupt. MBUF (w) : Master IIC data shift register write; after START and before STOP condition, this register will resume MTV012E's transmission to the IIC bus. Master IIC data shift register read; after START and before STOP condition, this register will resume MTV012E's receiving from the IIC bus.
MBUF (r) :
WDT (w) : Watchdog timer control register. WEN =1 Enables the watchdog timer. WCLR =1 Clears the watchdog timer. CLRDDC =1 Clears the DDC2 flag. WDT2: WDT0 = 0 Overflow interval = 8 x 0.25 sec. =1 Overflow interval = 1 x 0.25 sec. =2 Overflow interval = 2 x 0.25 sec. =3 Overflow interval = 3 x 0.25 sec. =4 Overflow interval = 4 x 0.25 sec. =5 Overflow interval = 5 x 0.25 sec. =6 Overflow interval = 6 x 0.25 sec. =7 Overflow interval = 7 x 0.25 sec. FIFO (w) : Writes FIFO contents.
SLVCTR (w) : Slave IIC block control. ENSLV =1 Enables slave IIC block. =0 Disables slave IIC block. SLVsel =1 Slave IIC connects to ISDA/ISCL. =0 Slave IIC connects to HSDA/HSCL. ESLVBI =1 Enables slave buffer interrupt. ESLVMI =1 Enables slave address match interrupt. SLVSTUS (r) : Slave IIC block status. WADR =1 The data in SLVBUF is a word address. SLVS =1 The slave block has detected a START; will be cleared when STOP is detected. SLVBI =1 SLVBUF has been loaded with a new data byte; reset by S/W reading SLVBUF. SLVMI =1 Slave block has detected the slave address match condition; cleared by S/W writing 0 to SLVMI. SLVINT (w) : Slave block interrupt. The SLVBI/SLVMI interrupt will set its flag, and, if the corresponding interrupt enable bit is set, the 8051 INT1 source will be driven by a zero level. Software MUST clear this register while serving the interrupt routine. SLVMI =1 No action. =0 Clears SLVMI. Slave IIC data latch.
MTV012E Revision 1.2 12/23/1998 12/14
SLVBUF (r) :
MYSON TECHNOLOGY
SLVADR (w) : Slave IIC address to which the slave block should respond.
MTV012E
4.0 Test Mode Condition
In normal application, users should not allow MTV012E to enter its test/program mode, outlined as follows: Test Mode A: RESET=1 & DA9=1 & DA8=0 & STO=0 Test Mode B: RESET falling edge & DA9=1 & DA8=0 & STO=1 Program Mode: RESET=1 & DA9=0 & DA8=1
5.0 INTERNAL EPROM
To program the internal EPROM, MTV012E must be running at a 4 to 6 MHz cycle time. The address of an EPROM location to be programmed is applied to Port1 (A0 - A7) and pins P2.0 - P2.4(A8 - A12) of Port2, while the code byte to be programmed is applied to DA0 - DA7. All other pins should be held at the level indicated in the following table. The overall programming characteristics are very similar to those of 87C52 with the exception that pin #30 and pin #31 are switched.
RST DA9 STOUT DA8 Mode Normal Reset 1 1 0 1 Program Code Data 1 0 P* VPP Program Lock Bit 1 0 P* VPP Verify Code 1 0 1 1 Note 1: VPP = 12.7V Note 2: P* is pulsed low for 100uS for programming. P2.7 P2.6 HBLANK VBLANK
X 1 1 0
X 0 1 0
X 1 1 1
X 1 1 1
6.0 ELECTRICAL PARAMETERS
6.1 Absolute Maximum Ratings at: Ta= 0 to 70 oC, VSS=0V Name Maximum Supply Voltage Maximum Input Voltage Maximum Output Voltage Maximum Operating Temperature Maximum Storage Temperature 6.2 Allowable Operating Conditions at: Ta= 0 to 70 oC, VSS=0V Name Supply Voltage Input "H" Voltage Input "L" Voltage Operating Freq.
Symbol VDD Vin Vout Topg Tstg
Range -0.3 to +6.0 -0.3 to VDD+0.3 -0.3 to VDD+0.3 0 to +70 -25 to +125
Unit V V V oC oC
Symbol VDD Vih1 Vil1 Fopg
Min. 4.0 0.7 x VDD -0.3 -
Max. 6.0 VDD +0.3 0.15 x VDD 15
Unit V V V MHz
MTV012E Revision 1.2 12/23/1998 13/14
MYSON TECHNOLOGY
6.3 DC Characteristics at: Ta=0 to 70 oC, VDD=4.0V ~ 6.0V, VSS=0V Name Symbol Condition Output "H" Voltage, except openVoh1 Ioh=-50uA drain pins, pins #16, 17, 29 Output "H" Voltage, pins #16, 17, 29 Voh2 Ioh=-1mA Output "L" Voltage Vol Iol=8mA Active Power Supply Current Idd Idle Power-Down RST Pull-Down Resistor Rrst VDD=5V Pin Capacitance Cio 6.4 AC Characteristics at: Ta=0 to 70 oC, VDD=4.0V ~ 6.0V, VSS=0V Name Symbol Crystal Frequency fXtal PWM DAC Frequency fDA PWM DAC Frequency fDA HS Input Pulse Width tHIPW VS Input Pulse Width tVIPW HS Input Pulse Width tHIPW VS Input Pulse Width tVIPW HSYNC to HBLANK Output Jitter tHHBJ H+V to VBLANK Output Delay tVVBD H+V to VBLANK Output Delay tVVBD VS Pulse Width in H+V Signal tVCPW VS Pulse Width in H+V Signal tVCPW
MTV012E
Min. 4 4
Typ.
Max.
Unit V V V mA mA uA Kohm pF
18 1.3 50 50
0.45 24 4.0 80 150 15
Condition fXtal=8MHz fXtal=12MHz fXtal=8MHz fXtal=8MHz fXtal=12MHz fXtal=12MHz fXtal=8MHz fXtal=12MHz fXtal=8MHz fXtal=12MHz
Min. 31.25 46.875 0.3 3 0.2 2
Typ. 8
Max. 31.62 47.43 12 8 5
16 10 32 20
Unit MHz KHz KHz uS US US US NS uS uS uS uS
6.0 PACKAGE DIMENSION
40 PIN PDIP 600 mil
52.197mm +/-0.127
MTV 012
1.981mm +/-0.254 1.270mm +/-0.254 0.457mm +/-0.127 2.540mm 15.494mm +/-0.254 13.868mm +/-0.102 1.778mm +/-0.127 0.254mm (min.) 0.254mm +/-0.102
3.81mm +/-0.127 3.302mm +/-0.254
5o~70
6o +/-3o 16.256mm +/-0.508
MTV012E Revision 1.2 12/23/1998 14/14

▲Up To Search▲

Price & Availability of MTV012E

	To Download MTV012E Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .